Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics

S. Nagaraj; K. Venkatramana Reddy; P. Anil Kumar

Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics

S. Nagaraj Department of ECE, SVCET, RVS NAGAR, Chittoor, AP, India;
K. Venkatramana Reddy Department of ECE, SVCET, RVS NAGAR, Chittoor, AP, India;
P. Anil Kumar Department of ECE, MTIET, Palamaner, Chittoor, AP, India

Keywords: Vedic Multiplier, CMOS, Adder, Ripple Carry Adder, Complementary Pass Transistor Logic(CPL)

Abstract

In this work we have designed and analyzed Vedic Multiplier for conventional CMOS and Complementary Pass Transistor Logic (CPL). Vedic Multiplier is designed for 4-bit and 8-bit using conventional CMOS gates and CPL gates. Their Speed, Area and Power is analyzed and compared. The design is implemented using HSPICE for 180nm Technology.

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Published

2020-11-30

Issue

Vol 12 No SUP 3 (2020): SAMRIDDHI: A Journal of Physical Sciences, Engineering and Technology

Section

Research Articles

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.